CHECKING CORRECTNESS OF HARDWARE RNG ARCHITECTURE SPECIFICATIONS




Abstract:
In this paper we will show one possible implementation of hardware randomness generator. The device in question is based on widely available electronic components comprised of double analogue comparator operating as a free running oscillator and RISC microcontroller used for post processing. Finally, we incorporated an USB interface for communication with the device in order to acquire and evaluate its practical use in cryptography. Data generated by our device show very good randomness characteristics and have high entropy.

CITATION:

IEEE format

I. Fermevc, S. Adamović, “Checking Correctness of Hardware RNG Architecture Specifications,” in Sinteza 2016 - International Scientific Conference on ICT and E-Business Related Research, Belgrade, Singidunum University, Serbia, 2016, pp. 179-182. doi:10.15308/Sinteza-2016-179-182

APA format

Fermevc, I., Adamović, S. (2016). Checking Correctness of Hardware RNG Architecture Specifications. Paper presented at Sinteza 2016 - International Scientific Conference on ICT and E-Business Related Research. doi:10.15308/Sinteza-2016-179-182

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